Binary To Bcd Verilog

In computer science, the double dabblealgorithm is used to convert binary numbers into binary-coded decimal (BCD) notation.^[1]^[2] It is also known as the shift-and-add-3 algorithm, and can be implemented using a small number of gates in computer hardware, but at the expense of high latency.^[3]

Algorithm[edit]

The algorithm operates as follows:

Module binarytoBCD (indata, ones, tens, hundreds) input. Binary to Bcd with Verilog. Each shift effectively doubles the value of the binary number in the four bit shift register which is going to hold the converted BCD digit. Each time a bit is.

Suppose the original number to be converted is stored in a register that is n bits wide. Reserve a scratch space wide enough to hold both the original number and its BCD representation; n + 4×ceil(n/3) bits will be enough. It takes a maximum of 4 bits in binary to store each decimal digit.

Then partition the scratch space into BCD digits (on the left) and the original register (on the right). For example, if the original number to be converted is eight bits wide, the scratch space would be partitioned as follows:

The diagram above shows the binary representation of 243₁₀ in the original register, and the BCD representation of 243 on the left.

The scratch space is initialized to all zeros, and then the value to be converted is copied into the 'original register' space on the right.

The algorithm then iterates n times. On each iteration, any BCD digit which is at least 5 (0101 in binary) is incremented by 3 (0011); then the entire scratch space is left-shifted one bit. The increment ensures that a value of 5, incremented and left-shifted, becomes 16 (10000), thus correctly 'carrying' into the next BCD digit.

Essentially, the algorithm operates by doubling the BCD value on the left each iteration and adding either one or zero according to the original bit pattern. Shifting left accomplishes both tasks simultaneously. If any digit is five or above, three is added to ensure the value 'carries' in base 10.

The double-dabble algorithm, performed on the value 243₁₀, looks like this:

Now eight shifts have been performed, so the algorithm terminates. The BCD digits to the left of the 'original register' space display the BCD encoding of the original value 243.

Another example for the double dabble algorithm – value 65244₁₀.

Sixteen shifts have been performed, so the algorithm terminates. The decimal value of the BCD digits is: 6*10⁴ + 5*10³ + 2*10² + 4*10¹ + 4*10⁰ = 65244.

Parametric Verilog implementation of the double dabble binary to BCD converter^[4][edit]

Parametric Verilog implementation of the double dabble binary to BCD converter, 18-bit example.^[5]

Reverse double dabble[edit]

The algorithm is fully reversible. By applying the reverse double dabble algorithm a BCD number can be converted to binary. Reversing the algorithm is done by reversing the principle steps of the algorithm:

The principle steps of the algorithms
Double dabble (Binary to BCD)	Reverse double dabble (BCD to binary)
For each group of input four bits: If group >= 5 add 3 to group Left shift into the output digits	Right shift into the output binary For each group of four input bits: If group >= 8 subtract 3 from group

Reverse double dabble example[edit]

The reverse double dabble algorithm, performed on the three BCD digits 2-4-3, looks like this:

16 Bit Binary To Bcd Verilog Code

Historical[edit]

In the 1960s, the term double dabble was also used for a different mental algorithm, used by programmers to convert a binary number to decimal. It is performed by reading the binary number from left to right, doubling if the next bit is zero, and doubling and adding one if the next bit is one.^[6] In the example above, 11110011, the thought process would be: 'one, three, seven, fifteen, thirty, sixty, one hundred twenty-one, two hundred forty-three', the same result as that obtained above.

References[edit]

^Gao, Shuli; Al-Khalili, D.; Chabini, N. (June 2012), 'An improved BCD adder using 6-LUT FPGAs', IEEE 10th International New Circuits and Systems Conference (NEWCAS 2012), pp. 13–16, doi:10.1109/NEWCAS.2012.6328944, S2CID36909518
^'Binary-to-BCD Converter: 'Double-Dabble Binary-to-BCD Conversion Algorithm''(PDF). Archived from the original(PDF) on 2012-01-31.
^Véstias, Mario P.; Neto, Horatio C. (March 2010), 'Parallel decimal multipliers using binary multipliers', VI Southern Programmable Logic Conference (SPL 2010), pp. 73–78, doi:10.1109/SPL.2010.5483001, S2CID28360570
^Abdelhadi, Ameer (2019-07-07), AmeerAbdelhadi/Binary-to-BCD-Converter, retrieved 2020-03-03
^Abdelhadi, Ameer (2019-07-07), AmeerAbdelhadi/Binary-to-BCD-Converter, retrieved 2020-03-03
^Godse, Deepali A.; Godse, Atul P. (2008). Digital Techniques. Pune, India: Technical Publications. p. 4. ISBN978-8-18431401-4.

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Binary To Bcd Conversion Verilog

Falconer, Charles 'Chuck' B. (2004-04-16). 'An Explanation of the Double-Dabble Bin-BCD Conversion Algorithm'. Archived from the original on 2009-03-25.